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<code>   ___ ___         _
  /   |   \ ___ __/ \__ ___  ___  /\__
  \  / \  // __>\_   _// __|/ __\/    \
   \_____/_\__ \  \_/  \___|\___/\_/\_/
          \____/		2.1</code>

====== About ======
WStech doc v2.1 made by Judge and Dox \\
Special thanks to -anonymous- contributor for some usefull info.

Released 26.03.2002 on Dox Homepage.

Comments/updates/infos please send to dox@space.pl (or well, to [[homepage@fensterbrett.org|me]])


===== What's new in version 2.1 =====
  * Correct info about CPU
  * Additional sound info
  * Correct info about timers (change VBL End interrupt to VBL Timer)
  * Better description about Serial Communication
  * Full info about EEPROMs

====== CPU ======
Bandai SPGY-1001 ASWAN 9850KK003  \\
NEC V30 MZ - fast version of V30 with internal pipeline (16 bytes prefatch buffer) running at 3.072 MHz.
V30 MZ is aprox 4 times faster than V30.   
The V30MZ performs pipeline processing internally, performing instruction fetch (prefetch), instruction decode, and
instruction execution in parallel. For this reason, it is difficult to determine what part of the program is currently being
executed by monitoring the output of the address bus for the instruction code fetch.
If there are conditional branch instructions, even in case branching does not occur, the address of the branch
destination is prefetched (only one time), so that further monitoring of the program is difficult.
The V30MZ has 8 prefetch queues (16 bytes)

There are a few other differences between V30MZ and V30 cpu (unsupported opcodes , different flag handling after mul/div).

====== Memory ======
20 bit addressing space = 1 Megabyte. Memory is splitted into 64KB blocks (segments/banks).
   	
===== Segments =====
^ $0 |  RAM  | 16 KB (WS) / 64 KB (WSC) internal RAM (see below) ||
^ $1 |  SRAM (cart)  | SRAM is BSI device BS62LV256TC - 256K(32Kx8) Static RAM - TSOP 0 - 70 c, 70 ns (http://www.bsi.com.tw/product/bs62lv256.pdf)  | FIXME |
| ||||
^ $2 |  ROM Bank  | initial bank = last  ||
^ $3 |  ROM Bank  | initial bank = last  ||
^ $4 |  ROM Bank  | initial bank = last - 11  ||
^ $5 |  ROM Bank  | initial bank = last - 10  ||
^ $6 |  ROM Bank  | initial bank = last - 9  ||
^ $7 |  ROM Bank  | initial bank = last - 8  ||
^ $8 |  ROM Bank  | initial bank = last - 7  ||
^ $9 |  ROM Bank  | initial bank = last - 6  ||
^ $A |  ROM Bank  | initial bank = last - 5  ||
^ $B |  ROM Bank  | initial bank = last - 4  ||
^ $C |  ROM Bank  | initial bank = last - 3  ||
^ $D |  ROM Bank  | initial bank = last - 2  ||
^ $E |  ROM Bank  | initial bank = last - 1  ||
^ $F |  ROM Bank  | initial bank = last  ||

        
Segments $2 and $3 are switchable using ports: 
| $C2 | Segment 2 |
| $C3 | Segment 3 |
Value written to port is ROM Bank number. $FF means last ROM bank (last 64 kbytes of ROM file), $FE  = last - 1 .. etc

Segements $4-$F thought Port $C0 using 

^ Bit  | ^7^6^5^4^3^2^1^0^
^ Data  | |  FOO  ||||  BAA  ||||


        $C0 - Segments 4-$F - 
        bits 0-3 of are bits 4-7 of ROM bank number in segments 4-$F
        Bits 0-3 are taken form segment number ( for example , IO[$C0]=$4E  -> segment 9 contains ROM bank $E9).

        FIXME - not sure if this is right ..
        

===== RAM Map =====

      $0000 - $1FFF                           WS/WSC
      $2000 - $3FFF    4 Col Tiles            WS/WSC
      -------------
      $4000 - $7FFF   16 Col Tiles Bank 0     WSC only
      $8000 - $BFFF   16 Col Tiles Bank 1     WSC only
      $C000 - $FDFF                           WSC only
      $FE00 - $FFFF   Palettes (WSC)          WSC only


===== under construction =====
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